1. Field of the Invention
The present invention relates generally to semiconductor devices, and in particular to configurations for reducing the current consumed in a refresh mode for holding data, such as a sleep mode or a power down mode, without causing an erroneous operation in a semiconductor memory device requiring refreshing of storage data. More specifically, the present invention relates to a configuration for reducing the current consumed in a refresh mode by a logic merged memory with a logic and a dynamic random access memory integrated on a single semiconductor chip.
2. Description of the Background Art
A conventional CMOS semiconductor device is reduced in transistor size, in particular, gate length of a MOS transistor (an insulated gate field effect transistor) to achieve high density and high integration. While a reduced power supply voltage is employed to ensure the reliability of such a microfabricated transistor and reduce the power consumption of the device, in order to achieve fast operation the MOS transistor is required to have a threshold voltage Vth reduced in absolute value as an operating power supply voltage is reduced.
A MOS transistor, however, conducts a current referred to as a sub threshold leakage current (referred to as an xe2x80x9coff leak currentxe2x80x9d hereinafter) between its source and drain even when it is turned off. When a threshold voltage is reduced in absolute value, an increased off leak current flows. Since an absolute value of a threshold voltage has a negative temperature-dependency and thus reduces as temperature rises, an increased operating temperature causes an increased off leak current and hence an increased direct current in the entirety of a large scale integrated circuit. In particular, in a dynamic semiconductor memory device, a current flowing in a standby state (a standby current) is disadvantageously increased.
In order to reduce current consumption in the standby state without degrading high speed operability, there has been conventionally proposed a hierarchical power supply configuration or an MT-CMOS (Multi Threshold-CMOS) configuration, as disclosed, e.g., in Japanese Patent Laying-Open No. 6-237164 and Ultra LSI Memory, by Ito 1994, published by Baihukan.
FIG. 60 shows an example of a conventional MT-CMOS configuration. In FIG. 60, cascaded CMOS inverters IV1-IV5 of five stages are shown as an internal circuit. An input signal IN fed to the first-stage inverter IV1 is at a low level in a standby cycle. CMOS inverters IV1-IV5 have an identical configuration and each includes a p channel MOS transistor PT and an n channel MOS transistor NT. MOS transistors PT and NT each are a low threshold voltage (L-Vth) MOS transistor with its threshold voltage reduced in absolute value.
For inverters IV1-IV5, there are provided a main power supply line 1 receiving a power supply voltage Vcc, a sub power supply line 3 coupled with main power supply line 1 via a leakage-cutting p channel MOS transistor PQ, a main ground line 2 transmitting a ground voltage Vss, and a sub ground line 4 connected to main ground line 2 via a leakage-cutting n channel MOS transistor NQ. Leakage-cutting MOS transistors PQ and NQ are an (M-Vth) MOS transistor which has a threshold voltage greater in absolute value than MOS transistors PT and NT have.
MOS transistor PQ has its gate receiving a control signal /xcfx86 and MOS transistor NQ has its gate receiving a control signal xcfx86. Control signal xcfx86 attains a high level in an active cycle in which the internal circuit operates, and control signal xcfx86 attains a low level in a standby cycle in which the internal circuit is set in a standby state. Control signal /xcfx86 attains a low level in the active cycle and a high level in the standby cycle.
In the internal circuit, odd-stage inverters IV1, IV3 and IV5 . . . have sources of their p channel MOS transistors PTs connected to main power supply line 1 and sources of n channel MOS transistors NTs connected to sub ground line 4. Even-stage inverters IV2, IV4, . . . have sources of their p channel MOS transistors PTs connected to sub power supply line 3 and sources of their n channel MOS transistors NTs connected to main ground line 2. An operation of the MT-CMOS configuration shown in FIG. 60 will now be briefly described with reference to the signal waveform diagram shown in FIG. 61.
In the standby cycle, control signal xcfx86 is at a low level and control signal /xcfx86 is at a high level, and input signal IN is at a low level. In this state, leakage cutting MOS transistors PQ and NQ are turned off. In odd-stage inverters IV1, IV3, and IV5, their p channel MOS transistors PTs are turned on and their n channel MOS transistors NTs are turned off, since input signal IN is at a low level. The p channel MOS transistors PTs have their sources connected to main power supply line 1 and the n channel MOS transistors NTs have their sources connected to sub ground line 4. When p channel MOS transistor PT transmits to a corresponding output node (or drain) a voltage of the power supply voltage Vcc level on main power supply line 1, its source and drain voltages are equalized and the transistor does not conduct.
The n channel MOS transistor NT receiving a low level signal at the gate, causes off leak current. Sub ground line 4 is connected to main ground line 2 via leakage cutting MOS transistor NQ having the relatively high threshold voltage M-Vth. Thus, when off leak currents from inverters IV1, IV3 and IV5 flow to sub ground line 4, leakage cutting MOS transistor NQ cannot discharge all of the off leak currents and a voltage level SVss on sub ground line 4 becomes higher than ground voltage Vss. The level of voltage SVss on sub ground line 4 is ultimately determined by a relationship between the amount of the leakage current discharged by leakage cutting MOS transistor NQ and the sum of all of the off leak currents from the inverter stages included in the internal circuit. When voltage SVss on sub ground line 4 becomes higher than ground voltage Vss, in odd-stage inverters IV1, IV3, IV5 their n channel MOS transistors NTs have their respective gates and respective sources reverse-biased, resulting in a further reduced off leak current.
In even-stage inverters IV2, IV4 . . . , input signal IN is at a high level.
Even-stage inverters IV2, IV4, . . . have their p channel MOS transistors PTs connected at the respective sources to sub power supply line 3 and their n channel MOS transistors NTs connected at the respective sources to main ground line 2. Thus, in even stage inverters IV2, IV4, . . . their n channel MOS transistors have their sources and drains both set at the ground voltage Vss level and thus do not conduct and cause no off leak current. The p channel MOS transistors PTs, however, cause off leak current. Between main power supply line 1 and sub power supply line 3, leakage-cutting MOS transistor PQ is set to have a threshold voltage of a relatively large absolute value (M-Vth). Thus, the amount of the leakage current from main power supply line 1 to sub power supply line 3 is determined by leakage cutting MOS transistor PQ, and voltage SVcc on sub power supply line 3 becomes lower than the power supply voltage Vcc level. The voltage SVcc level on sub power supply line 3 is ultimately determined by a relationship between the leakage current from leakage cutting MOS transistor PQ and the sum of all of the off leak currents in even-stage inverters IV2, IV4, . . . . When voltage SVcc is lower than power supply voltage Vcc, in even-stage inverters IV2, IV4, . . . their p channel MOS transistors PTs have the respective gates and respective sources reverse-biased, resulting in a further reduced off leak current.
In the active cycle, control signal xcfx86 attains a high level and control signal /xcfx86 attains a low level, leakage cutting MOS transistors PQ and NQ are turned on, main power supply line 1 is connected to sub power supply line 3, and main ground line 2 is connected to sub ground line 4. Thus, voltage SVcc on sub power supply line 3 attains the power supply voltage Vcc level and voltage SVss on sub ground line 4 attains the ground voltage Vss level. In the active cycle, input signal IN varies with an operating state. The MOS transistors of inverters IV1-IV5 . . . configuring the internal circuit are low threshold voltage MOS transistors and thus operate at high speed. Leakage cutting MOS transistors PQ and NQ have their current supplying ability set to a large value, in order to sufficiently guarantee the operation of the internal circuit.
By arranging a power supply line and a ground line in hierarchical configuration of the main and sub power supply lines and the main and sub ground lines, the power supply line/ground line has an impedance thereof increased to reduce a leakage current in the standby cycle, and in the active cycle the power supply line/ground line has an impedance thereof reduced to allow a fast operation owing to the low threshold voltage MOS transistors in the internal circuit. A semiconductor circuit device providing a reduced current consumption in the standby cycle and also operating at high speed in the active cycle is to be implemented.
With the conventional MT-CMOS configuration, when an active cycle starts, control signals xcfx86 and/xcfx86 are driven to high and low levels, respectively, and responsively leakage cutting MOS transistors PQ and NQ of FIG. 60 turn on. Thus, a period of time is required from the start of the active cycle until voltages SVcc and SVss on sub power supply line 3 and sub ground line 4 respectively reach power supply voltage Vcc and ground voltage Vss and are stabilized. The internal circuit cannot operate while voltages SVcc and SVss on sub power supply line 3 and sub ground line 4 are unstable. Thus, as shown in FIG. 62, a period of time is required before the internal circuit actually operates after an active cycle starts, and fast operation can not be achieved. Operating the internal circuit with unstable voltages SVcc and SVss would result in an erroneous operation, and accordingly a period of time required for stabilizing voltages SVcc and SVss and additional margin must be considered in determining a timing at which the internal circuit starts to operate.
Furthermore, as shown in FIG. 60, the conventional MT-CMOS configuration requires input signal IN to be set at a predetermined logic level in the standby cycle. According to the logic level of input signal IN in the standby cycle, it must be determined where the internal circuit""s power supply and ground lines are connected. For a random logic and a register circuit storing data indicative of operating conditions and such, however, input signals IN cannot have a predetermined logic level in the standby cycle, and the MT-CMOS configuration as shown in FIG. 60 can not be employed.
If a semiconductor device is a dynamic semiconductor memory device (referred to as a DRAM hereinafter), when no access is made for a relatively long period of time and a sleep mode is set, DRAM is set to a self refresh mode. In the self refresh mode, the DRAM internally, periodically refreshes the data stored in memory cells.
When self refresh operation is in effect performed, the DRAM enters an active cycle, and when the refresh operation completes, the DRAM enters a standby cycle. That is, the DRAM in the self refresh mode enters the active cycle at predetermined intervals. Thus, in the self refresh mode the data in memory cells are internally refreshed to merely hold the data. This results in a disadvantageous current consumption. In order to reduce current consumption, a longer refresh interval is required. However, an unnecessarily long refresh interval results in the data in memory cells being destroyed before refresh operation is performed, and the data cannot be held.
An object of the present invention is to provide a semiconductor device capable of reducing a current consumption in a standby state without degrading its fast operability.
Another object of the present invention is to provide a semiconductor device capable of reducing a current consumption in a self refresh mode.
Still another object of the present invention is to provide a semiconductor device capable of reducing a current consumption in a standby mode without negatively affecting its normal operation and data holding capability.
In one aspect, the semiconductor device according to the present invention includes a plurality of memory cells requiring refreshing of the storage data within a predetermined period of time, refresh-related circuitry for performing an operation of refreshing the data stored in the plurality of memory cells in a refresh mode, peripheral circuitry different from the refresh-related circuitry and performing at least an operation related to accessing to the plurality of memory cells, a first power supply circuit for supplying an operating power supply voltage to the refresh-related circuitry, a second power supply circuit provided separately from the first power supply circuit for supplying an operating power supply voltage to the peripheral circuitry, and a power supply control circuit responsive to an operation mode designation signal for adjusting an impedance of at least the second power supply circuit. The power supply control circuit includes a circuit for setting the first and second power supply circuits into different voltage supplying states when the operation mode designation signal designates the refresh mode and for setting the first and second power supply circuits in the same voltage supplying state when the operation mode designation signal designates a normal mode different from the refresh mode.
In a second aspect, the semiconductor device includes a plurality of memory cells having their storage data refreshed within a predetermined period of time, a register circuit receiving a power supply voltage of a power source node for storing information related to an operation of accessing the plurality of memory cells, a register capacitor provided corresponding to the register circuit for holding information stored in the register circuit, and a control circuit for periodically refreshing information stored in the register capacitor when an operation mode designation signal designates a refresh mode.
In a third aspect, the semiconductor device includes a memory cell array of a plurality of memory cells having a predetermined storage capacity and having the data stored therein refreshed within a predetermined period of time, a circuit for receiving and storing an address designating a refresh region to be refreshed when a refresh mode of performing a refresh operation is designated in response to an operation mode designation signal, a refresh address generation circuit for generating a refresh address to address a memory cell to be refreshed in a region designated by the refresh region designating address when the operation mode designation signal designates the refresh mode, a refresh timer outputting a refresh request requesting refreshing of the data stored in the memory cells at a predetermined period, and refresh-related circuitry responsive to the refresh request from the refresh timer for refreshing the data stored in the memory cells of the refresh address.
In the refresh mode, supply of a power source voltage to the peripheral circuitry can be stopped to save the current consumed by the peripheral circuitry in the refresh mode. In the normal mode, the refresh-related circuitry and the peripheral circuitry can both receive a power supply voltage to prevent the power supply voltage from varying upon switching between an active cycle and a standby cycle, so that an internal circuit can start to operate at a fast timing.
In the refresh mode, periodical refreshing of the information stored in the register capacitor holding the data of the register circuit allow power supply to the register circuit to be intermittently stopped in the refresh mode, resulting in reduced current consumption in the refresh mode.
In the refresh mode, refreshing of memory cells only in a predetermined address region allows the number of memory cell rows refreshed or the frequency of refresh operations to be reduced to implement a reduced current consumption.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.